Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding ic

ABSTRACT

A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a division of application Ser. No.08/670,179, filed Jun. 20, 1996, entitled PROCESS FOR FORMING ANINTEGRATED CIRCUIT COMPRISING NON-VOLATILE MEMORY CELLS AND SIDETRANSISTORS OF AT LEAST TWO DIFFERENT TYPES, AND CORRESPONDING IC, whichprior application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a process for forming anintegrated circuit comprising non-volatile memory cells and peripheraltransistors of at least two different types.

[0004] Specifically, the present invention relates to a processproviding for the implementation in a monocrystalline silicon substrateof at least one matrix of memory cells. In each memory cell a floatinggate and a control gate, both electroconductive, are mutuallyelectrically insulated by means of an intermediate dielectricmultilayer. There is also provided simultaneous formation, in zonesperipheral to the matrix, of at least first and second MOS transistortypes.

[0005] The present invention also relates to an integrated circuit ofthe above mentioned type comprising non-volatile memory cells having anintermediate dielectric multilayer and at least two types of peripheraltransistors.

[0006] 2. Discussion of the Related Art

[0007] As is known in the field of electronic semiconductor technology,in order to reduce the area of integrated circuits there is a tendencytowards ever greater integration scales with a reduction of componentsizes. This has led to improvement of the quality of the materials usedand to optimization of the processes for their formation.

[0008] The present invention relates to the field of the development ofthe techniques of formation of dielectric materials in a singleintegrated circuit, and in the formation of layers of differentthickness and composition which perform different functions. On one handthe dielectric materials act as insulators providing electricalinsulation of conductive layers and creating a barrier againstcontaminating substances coming from the outside environment, while onthe other hand the dielectric materials act as active dielectricsallowing the passage of charges between layers of conductive materials.

[0009] In order to improve the quality and functionality of the abovementioned dielectrics it has been proposed in relatively recent times toprovide multiple superimposed layers, in particular using layers ofsilicon oxides and/or silicon nitrides.

[0010] In the specific field of application of the present inventionthere are provided integrated memory circuits including, in addition toa plurality of memory cells arranged in one or more matrixes, externalor peripheral circuits in which components are structurally similar tothe cells and are provided by the same technology. Specific reference ismade to MOS transistors.

[0011] Non-volatile memories, to which specific reference is made in thepresent invention, comprise different classes of devices or productswhich differ from each other by the structure of the individual memorycell and the type of application. Specifically reference is made toread-only memories which can be electrically programmed and erased(Erasable Programmable Read Only Memories) and specifically EPROM,EEPROM or FLASH. These types of memories can be distinguished from oneanother as some of them are both erasable and electrically programmable,while others require, e.g., ultraviolet light to be erased. For datastorage, memory cells comprise in all cases a floating-gate MOStransistor integrated on a substrate usually of monocrystalline silicon.The amount of charge contained in the floating gate determines thelogical state of the cell. Non-volatile memory cells are programmed in adiscrete number of logical states allowing memorization of one or morebits per cell. In standard cells, for example, programming is providedin two logical states, written and erased, with memorization of one bitper cell.

[0012] The floating gate of electroconductive material, normallypolysilicon, i.e. polycrystalline silicon or “poly”, is completelysurrounded by insulating material. In particular, over the floating gatea dielectric layer, so-called intermediate dielectric or interpoly,insulates the floating gate from an overlying control gate also ofelectroconductive material. The control gate can consist alternativelyof a single polysilicon layer or of a double polysilicon-silicide layerand is coupled electrically to a programming terminal.

[0013] As known to those skilled in the art, the interpoly dielectric isparticularly critical in terms of charge retention. Development of thetechnology has revealed as particularly advantageous the use of amultilayer intermediate dielectric. This preserves the insulatingcharacteristics of the intermediate layer while avoiding the problem ofloss of charge from the floating gate to the control gate, whether overthe long term or when a high programming potential is applied to thecontrol gate. In particular, as known to those skilled in the art, thisclass of intermediate dielectrics comprises a triple layer of siliconoxide, silicon nitride and silicon oxide, the so-called ONO. Asdescribed e.g. in U.S. Pat. No. 5,104,819, after formation of anunderlying silicon oxide layer and deposition of silicon nitride, anupper silicon oxide layer is formed by deposition instead of by theconventional oxidation of the underlying nitride. This type ofdielectric achieved has good charge retention capability and increasedcapacitive coupling between floating gate and control gate.

[0014] Regarding the so-called external or peripheral transistors, theyare incorporated in circuits outside the memory cell matrix, e.g.,logical, or matrix control circuits. Specifically in the framework ofthe present invention, reference is made, as indicated above, to MOStransistors.

[0015] MOS transistors include an active dielectric, the so-called gatedielectric, placed between the substrate and a gate of electroconductivematerial, normally polysilicon. The thickness of this dielectricdetermines the type of transistor formed, in terms of electricalproperties. In the same circuit is sometimes integrated two types oftransistors of the external circuitry having gate dielectrics ofdifferent thicknesses. Usually the active dielectric consists of asilicon oxide layer formed at a high temperature by oxidation of thesubstrate.

[0016] To minimize the number of production process steps of the entireintegrated circuit it is known to make the memory cells and peripheraltransistors simultaneously, as mentioned above. Specifically, thepresent invention falls within a class of processes in which thepolysilicon layer making up the gate of the peripheral transistorscorresponds to the formation process step in which the control gatepolysilicon layer of the memory cells is formed. In these processes theintermediate dielectric of the memory cells and the gate dielectric ofthe transistors of the circuitry are also formed simultaneously.

[0017] A known process, in which it is necessary to form two types ofperipheral transistors with differentiated gate oxide thickness,comprises essentially the following steps:

[0018] formation of a first polysilicon layer of the floating gate andof the intermediate dielectric, after formation of a gate silicon oxidelayer of the cells;

[0019] removal of the above mentioned layers from the zones in which thetransistors of the circuitry are formed;

[0020] formation, by means of high-temperature substrate oxidation, of asilicon oxide layer in the areas in which the peripheral transistors areto be formed;

[0021] removal of the silicon oxide layer from the areas of the secondtransistor type;

[0022] formation, again by substrate oxidation, of another silicon oxidelayer in the areas of both types of transistor; and

[0023] formation of a second polysilicon layer of the control gate ofthe cells which also constitutes the gate of the peripheral transistors.

[0024] Recently, in the framework of the research for new types ofdielectrics using MOS transistors, there was proposed use of a gatedielectric comprising, in addition to a silicon oxide layer achieved byhigh-temperature thermal oxidation, an overlying layer also of siliconoxide but achieved by deposition. The benefits of such a compositedielectric are described for example in an article entitled “Thin CVDstacked gate dielectric for ULSI technology” by Hsing-Huang Tseng et al.IEDM Technical Digest, page 321-324, 1993.

[0025] In U.S. Pat. No. 5,104,819 mentioned above there is disclosedformation of a memory cell matrix having ONO type interpoly dielectricand peripheral transistors with gate dielectric including anotherdeposited silicon oxide layer. The deposited silicon oxide layer of theintermediate dielectric multilayer of the cells also constitutes thegate dielectric upper layer of the peripheral transistors and is formedsuccessively over a first gate thermal silicon oxide layer.

[0026] This manufacturing process however only permits formation of asingle type of peripheral transistor. In addition the silicon oxidedeposited to complete the gate dielectric is not good quality if itsdeposition is not followed by a so-called thermodynamic annealingprocess, as indicated to be necessary in the above mentioned article.

[0027] The object the present invention is to conceive a process for theformation of non-volatile memory cells and peripheral transistorspermitting achievement of a gate dielectric and an intermediatedielectric of good quality, in order to achieve an integrated circuithaving characteristics of great reliability and functionality.

[0028] Another object is to provide this circuit while minimizing thenumber of process steps and thus the production costs.

[0029] Another object is to provide a process which is particularlyflexible and usable, for example, in the simultaneous formation ofperipheral transistors having different gate dielectrics.

SUMMARY OF THE INVENTION

[0030] In accordance with the present invention a process for theformation of an integrated circuit in a monocrystalline siliconsubstrate calls for the provision of at least one matrix of non-volatilememory cells in each of which a floating gate and a control gate, bothelectroconductive, are electrically insulated from each other by meansof an intermediate dielectric multilayer comprising a lower siliconoxide layer, an intermediate silicon nitride layer and an upper siliconoxide layer. The process also comprises simultaneous realization inperipheral zones of the matrix of at least first and second transistortypes each having a gate dielectric of a first and second thickness,respectively. There is considered in particular a process of the type inwhich the gate dielectrics of the transistors are formed simultaneouslywith the intermediate dielectric multilayer of the memory cells.

[0031] In accordance with the present invention, after formation of thefloating gate with a gate oxide layer and a polycrystalline siliconlayer as well as formation of the lower silicon oxide layer and of theintermediate silicon nitride layer, formation of the intermediatedielectric multilayer and of the gate dielectric calls for the followingprocess steps:

[0032] removal from the zones peripheral to the matrix of the abovementioned layers;

[0033] formation of a first silicon oxide layer over the substrate inthe areas of both types of transistors;

[0034] removal of the first silicon oxide layer from the areas assignedonly to the transistors of the second type;

[0035] deposition of said upper silicon oxide layer over the memorycells, over the first silicon oxide layer in the areas of thetransistors of the first type and over the substrate in the areas of thetransistors of the second type; and

[0036] formation of a second silicon oxide layer in the areas of bothtypes of peripheral transistors.

[0037] In accordance with one embodiment of the invention, formation ofthe first and second silicon oxide layers takes place by means of ahigh-temperature treatment in an oxidizing ambient. The gate dielectriclayer of all the peripheral transistors is therefore composed of anunderlying silicon oxide layer formed by means of thermal treatment,having differentiated thickness, and an overlying silicon oxide layerdeposited and densified by the above mentioned thermal treatment.

[0038] The gate dielectrics formed can be advantageously nitridized atthe end of their formation if desired.

[0039] The present invention solves the problems of the prior art byutilizing a process for the formation of an integrated circuitcomprising non-volatile memory cells and peripheral transistors of thetype described above and defined in the accompanying claims.

[0040] The present invention also solves the problems of the prior artby an integrated circuit comprising non-volatile memory cells andperipheral MOS transistors of at least a first and a second types.

[0041] The advantages of the formation process in accordance with thepresent invention are set forth in the Detailed Description of anembodiment thereof given below by way of non-limiting example withreference to the annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The invention will be better understood and appreciated from thefollowing detailed description of illustrated embodiments thereof, andthe accompanying drawings, in which:

[0043]FIGS. 1a-1 e show diagrammatic cross section views of successivesteps of a process for the formation of non-volatile memory cells andperipheral transistors of a first and a second type in accordance withthe present invention.

DETAILED DESCRIPTION

[0044] The description of a formation process for memory cells andperipheral transistors in accordance with the present invention is givenbelow with reference to one preferred embodiment of the presentinvention as shown in FIGS. 1a-1 e. These figures show unscaleddiagrammatic cross section views and illustrate in successive steps aformation process for a non-volatile memory cell and at least first andsecond peripheral MOS transistors. The partial structures of the celland the transistors are indicated respectively by reference numbers 1, 2and 3. The regions R1, R2 and R3 represent the zones in which are formedthe cell 1 and the transistors 2 and 3.

[0045] The two transistors are distinguished from each other by the gatedielectric thickness, which is greater for the first transistor than forthe second. In the memory circuit for example they representrespectively a high-voltage transistor and a low-voltage transistor.

[0046] There are shown in detail only the more significant process stepsfor the present invention, regarding the formation of the intermediatedielectric of the cell and the gate dielectric of the transistors.

[0047] The intermediate dielectric of the memory cell in accordance withthis embodiment of the resent invention consists of a triple layercomprising silicon oxide, silicon nitride and silicon oxide insuccession.

[0048] The diagrammatic structure of the memory cell 1 is consistentwith that of any non-volatile memory cell whether EPROM, EEPROM orFLASH, and consists of a floating gate MOS transistor. The peripheraltransistors 2 and 3 are also MOS type in accordance with the presentinvention. The process to which reference is made in the followingdescription of this embodiment is a MOS type process, preferablyperformed with CMOS technology.

[0049] The initial steps of a process of formation of memory cells andperipheral transistors, not shown in the figures because it isconventional, comprise defining insulation regions on a substrate 4 ofsemiconductor material, usually monocrystalline silicon, where a thicksilicon oxide layer, so-called field oxide, is formed and which delimitsactive area regions. It is noted that the cross sections shown in thefigures are contained entirely in active area regions and therefore thefield oxide is not visible.

[0050] Successively, both in active area regions in which the memorycells will be formed and in external regions in which the peripheraltransistors will be formed, and in particular in regions R1, R2 and R3of FIGS. 1a-1 e, silicon oxide, indicated by 5 in the figures, is grownby means of high-temperature thermal oxidation of the substrate. Thelayer 5 represents the so-called gate oxide of the memory cells. Thegate oxide layer of the cells is thin to allow transfer of the chargebetween the substrate and the floating gate by means of known physicalmechanisms. The mechanism used which depends on the type of non-volatilememory used. The gate oxide layers thickness can, vary between 70 Å and250 Å, depending on the type of non-volatile memory cells and theprogramming and associated erasure mechanism.

[0051] Over this gate oxide layer 5 of the cells is formed a first layerof electroconductive material, indicated in FIG. 1a by 6 and which willconstitute the floating gate of the cell 1. The layer 6 consistscommonly of a first polycrystalline silicon layer, known briefly as poly1, and is usually deposited over the entire silicon chip on which theintegrated circuit is formed.

[0052] The process continues with formation of the lower part of theintermediate dielectric layer of the memory cells. A silicon oxide layer7 is formed alternatively by Chemical Vapor Deposition (CVD) or by meansof high-temperature oxidation of the polysilicon layer 6. In addition asilicon nitride layer 8 is deposited by the CVD technique.

[0053] Some steps allow partial definition of the final structure of thecell, by means of removal in some zones of one or more layers from amongthose described above. These steps are specific for each differentnon-volatile memory type, and are not described here for the sake ofsimplicity.

[0054] In accordance with this embodiment of the present invention,before formation of the upper part of the intermediate dielectric of thecells, the layers 7 and 8 of the intermediate dielectric, thepolysilicon layer 6 and the gate oxide layer 5 of the cell 1 are removedin succession from the active peripheral areas, i.e. the regions R2 andR3 in which the peripheral transistors are to be formed. Removal takesplace by means of a photolithographic technique of masking andsuccessive chemical etching, at the end of which the mask ofphotosensitive material, usually a resin, is removed. FIG. 1a shows thestructure of the memory cell 1 and the regions R2 and R3 assigned to thetransistors 2 and 3 after performing this process step.

[0055] Advantageously, removal of the mask used for the precedingetching can be followed by a step of cleaning the surface of the entirechip, preferably by means of acid etching, e.g., in hydrofluoric acid(HF). This step has the purpose of eliminating any possible residues ofthe mask which, being of organic material, introduces impurities,especially on the exposed surface of the substrate in the peripheralregions R2 and R3. The silicon nitride layer 8 of the intermediatedielectric is not damaged by an etching of the above mentioned type.

[0056] A silicon oxide layer, indicated in FIG. 1b by 9, is formed inthis step of the process at least in the areas R2 and R3 of theperipheral transistors. Preferably, this formation-step comprises anoperation of oxidation in an oxidizing ambient at high-temperature. Thislayer 9 of silicon oxide is of the so-called thermal type because it isachieved by means of a thermodynamic process of raising the temperature.The substrate is oxidized superficially in the active areas R2 and R3 ofthe transistors 2 and 3. The oxidation of the exposed surface of thesilicon nitride layer 8 of the cell 1 due to this operation isnegligible. The thermal oxide layer 9 will constitute part of the gatedielectric of the transistor 2.

[0057] The high-temperature oxidation treatment is preferably performedin an oxidizing ambient in an atmosphere containing oxygen (O₂) and/orsteam (H₂O) and at a temperature between 750° C. and 950° C.

[0058] The next step is masking the regions R1 and R2, of the cell 1 andthe first transistor 2, to allow removal by means of a photolithographictechnique and successive chemical etching of the silicon oxide layer 9from the region R3 assigned to formation of the second transistor 3.FIG. 1c shows the three regions as they appear after removal of themask.

[0059] In accordance with a preferred embodiment of the presentinvention the above mentioned removal of the layer 9 takes place ifperformed in two steps. First the silicon oxide layer 9 is partiallyremoved from the region R3. The mask used is then removed and theetching of the surface of the silicon oxide layer 9 is continued untilcomplete removal of the layer so as to leave exposed the surface of thesubstrate in the region R3. This second etching step cleans the surfaceof the nitride layer 8 in the region R1 and the oxide layer 9 in theregion R2 of the first transistor 2 of the possible contamination causedby the etching mask applied previously.

[0060] The intermediate dielectric of the cells is completed in the nextprocess step with formation by deposition of a silicon oxide layer 10,as shown in FIG. 1d. Deposition can take place by means of any of thechemical vapor deposition techniques and preferably by means of a HighTemperature Oxidation (HTO) technique, i.e., any of the high-temperatureCVD techniques. As a chemical source there can be chosen one of theconventional ones, e.g., tetraethylorthosilicate, known to those skilledin the art as TEOS. The thickness of this deposited silicon oxide layer10 is preferably between 50 Å and 250 Å. Its value depends on that ofthe underlying intermediate dielectric layers of the cell 1.

[0061] As shown in FIG. 1d the layer 10 is deposited not only in theregion R1 of the matrix but also in the peripheral regions R2 and R3where it will constitute the upper part of the gate dielectric of thefirst and second peripheral transistors 2 and 3.

[0062] In the next step to complete the gate dielectrics of theperipheral transistors, an additional silicon oxide layer is formed inthe active areas both of the first transistor 2 and of the secondtransistor 3. The formation is performed in particular by means of anoxidation operation with a high-temperature treatment in oxidizingambient to induce oxidation of the substrate surface. The thermalsilicon oxide layer formed in this step is indicated by 11 in FIG. 1e.It represents the lower layer of the gate dielectric, which is in directcontact with the substrate because it is the result of oxidation of thesubstrate itself. It is noted that the line of demarcation between thelayers 11 and 9 of the first transistor 2 is drawn symbolically with abroken line since the two layers after their formation are essentiallyindistinguishable.

[0063] The oxidation operation for formation of the thermal siliconoxide layer 11 advantageously permits the simultaneous densification ofthe overlying deposited silicon oxide layer 10.

[0064] Preferably, growth of an additional silicon oxide layer 12 (notshown) takes place by using parameters similar to those chosen above forformation of the silicon oxide layer 10. Therefore, this step isperformed preferably in an oxidizing ambient at a temperature between750° C. and 950° C. and in an atmosphere containing at least one of thefollowing gasses: oxygen (O₂) and steam (H₂O).

[0065] The thickness values of the gate dielectrics of the first andsecond transistors, preset on the basis of the specific-desiredapplication, are achieved in this step.

[0066] Formation of the intermediate dielectric multilayer of the cell 1and the gate dielectric of the peripheral transistors 2 and 3 inaccordance with one embodiment of the present invention is completed bya nitridizing process performed by means of annealing in an ambientcontaining N₂O, to further increase the quality and reliability of thegate dielectrics.

[0067] The gate dielectric of both the peripheral transistors 2 and 3therefore comprises, in the preferred embodiment of the presentinvention, a double layer. Specifically a thermal silicon oxide layer,11 and 9 or 11 respectively for the first and second transistors, is indirect contact with the substrate and a deposited silicon oxide layer isoverlying. The latter appears in both the transistors as an extension ofthe upper silicon oxide layer of the intermediate dielectric multilayerof the cell 1.

[0068] In accordance with one embodiment of the present invention theoverall thicknesses of the gate oxides of both types of transistor areindicatively between 70 Å and 350 Å. The thermal oxide thicknesses alsofall within this range.

[0069] After the above described formation of the intermediatedielectric multilayer of the cell and the gate dielectric of theperipheral transistors, completion of the cell and the transistors takesplace through standard process steps. In particular a second polysiliconlayer, or poly 2, and if desired a silicide layer are deposited and thenpatterned for the simultaneous formation of the control gate of the celland of the gate of the transistors. The process is completed byappropriate implantations, formation of a passivation layer and of theinterconnections by means of opening of contacts, and deposition of oneor more metallization layers.

[0070] Therefore in the process in accordance with one embodiment of thepresent invention the gate dielectric of the transistors is not formedafter the formation of the intermediate dielectric of the cells.Deposition of the last silicon oxide layer of the intermediatedielectric allows simultaneously achieving the gate dielectric upperlayer of the peripheral transistors. Advantageously, in accordance withone embodiment of the present invention, in the transistors 2 and 3 thefinal thermal oxide layer 11 is formed after the overlying depositedoxide layer 10. This permits formation of the thermal oxide layer andsimultaneous densification, as mentioned above, of the layer 10 withoutfurther steps such as thermodynamic annealing processes which areessential in the prior art for curing the deposited layer and to ensureoperation of the device.

[0071] The proposed solution, in which the deposited silicon oxide layer10 is then densified during at least one successive oxidation step, thusprovides gate dielectrics with better quality both in terms of defectsand in terms of electrical qualities.

[0072] The use of a double layer for formation of gate dielectrics whoseupper part is deposited prevents formation of defects in the gatedielectric if considered as a whole. Indeed, a defect in one of thelayers is covered by the other and the simultaneous presence of twodefects at exactly the same point in the layer is highly improbable.

[0073] Furthermore the upper layer being deposited conforms to theunderlying structures, allowing covering of irregular growths of oxidesin critical positions, e.g., of the field oxide layer at its edges.

[0074] It should be remembered that the thermal oxide and the oxidedeposited in accordance with the disclosed embodiment of the presentinvention are distinguishable by means of electrical, physical andoptical measurements because they have different dielectric constants.

[0075] It is noted that the process in accordance with the disclosedembodiment of the present invention has the advantage of allowingformation of distinct layers of silicon oxide whose thicknesses can bechosen independently. The only fixed value for formation of the layersmaking up the gate dielectric of the transistors is that of thedeposited oxide layer 10, whose thickness should be determined, as knownto those skilled in the art and as mentioned above, on the basis of therelative thickness of the other two layers contained in the intermediatedielectric of cell 1 to ensure good operation thereof.

[0076] The process in accordance with the disclosed embodiment of thepresent invention is particularly simple and does not presentmanufacturing difficulties.

[0077] Another advantage of the described process is the flexibility inparticular in the use of optional cleaning steps, described above in theexplanation of the individual process steps, for optimization of thefunctionality of the dielectrics.

[0078] Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description is by wayof example only and is not intended as limiting. The invention islimited only as defined in the following claims and the equivalentsthereto.

What is claimed is:
 1. An integrated circuit on a monocrystallinesubstrate, the integrated circuit comprising: a matrix of non-volatilememory cells, each non-volatile floating memory cell having a floatinggate and a control gate, both gates being electroconductive, and anintermediate dielectric multilayer disposed between the floating gateand control gate for electrically insulating the floating gate and thecontrol gate from one another, the intermediate dielectric multilayerincluding at least a first silicon oxide layer; and at least one firstand one second transistor type formed in zones of the substrateperipheral to the matrix of non-volatile memory cells and havingmultilayer gate dielectrics of a first and second thickness,respectively, wherein the multilayer gate dielectric of both the firsttype and the second type of peripheral transistors include a secondsilicon oxide layer formed by means of a thermal treatment, and a thirdsilicon oxide layer overlying the second silicon oxide layer, the thirdsilicon oxide layer being densified by said thermal treatment.
 2. Theintegrated circuit of claim 1, wherein said third silicon oxide layerand said first silicon oxide layer of the intermediate dielectricmultilayer are the same layer.
 3. The integrated circuit of claim 1,wherein said transistors of the first and the second type are highvoltage and low voltage transistors, respectively, and said secondthickness of the gate dielectric of the second transistor type is lessthan said first thickness of the gate dielectric of the first transistortype.
 4. The integrated circuit of claim 1, wherein the thickness ofsaid multilayer gate dielectric of said second transistor type is lessthan that of said multilayer gate dielectric of said first transistortype.
 5. The integrated circuit of claim 1, wherein the multilayer gatedielectrics of the first and second types are nitridized to increase thequality and reliability of the gate dielectrics.
 6. The integratedcircuit of claim 1, wherein the thickness of said first silicon oxidelayer is between 50 Å and 250 Å and said first thickness and said secondthickness of the gate dielectrics are between 70 Åand 350 Å.
 7. Anintegrated circuit comprising: a substrate; at least one memory cellformed in the substrate, the memory cell having a floating gate, acontrol gate, and a multilayer dielectric disposed on the floating gateand the control gate and including a deposited layer, the multilayerdielectric insulating the floating gate from the control gate; a firsttransistor formed in the substrate in a first area of the substrateperipheral to the at least one memory cell, the first transistor havinga gate dielectric comprising: the deposited layer; a first layerunderlying the deposited layer of the first transistor, formed bythermal oxidation of the substrate; and a second layer underlying thedeposited layer of the first transistor, formed by thermal oxidation ofthe substrate; and a second transistor formed in the substrate in asecond area of the substrate peripheral to the at least one memory cell,the second transistor having a gate dielectric comprising: the depositedlayer; and a first layer underlying the deposited layer of the secondtransistor, formed by thermal oxidation of the substrate.
 8. Theintegrated circuit of claim 7, wherein the at least one memory cell andthe first and second transistors are MOS transistors.
 9. The integratedcircuit of claim 7, wherein the first layer underlying the depositedlayer of the first transistor and the first layer underlying thedeposited layer of the second transistor are different regions of thesame layer, the layer being formed on the surface of the substrate.